Deep learning model for 3D profiling of HAR features using high-voltage CD-SEM
3D devices require 3D metrology
The growing need for 5G connectivity, Internet of Things (IoT), and big data is driving new growth in the semiconductor industry as the capability to store and process more data requires a large number of low-cost, high-performance semiconductor devices. Advanced semiconductor devices have moved from simple planar structures to complex three-dimensional (3D) structures, and one of the biggest developments is the 3D NAND memory.
To decrease the cost-per-bit, 3D-NAND manufacturers continue to increase the aspect ratio of channel holes. But it has become more difficult to etch the high-aspect-ratio (HAR) holes straightly as the etching process may cause defects like tilting, bowing, and twisting (see Figure 1) which will affect the device performance and the wafer yield. Therefore, metrology techniques are also required to be 3D to measure the geometry of the HAR hole.
